1. Field of the Invention
This invention relates generally to marking techniques for semiconductor substrates. More specifically, the present invention relates to methods and apparatus for marking and identifying defective die sites on semiconductor mounting substrates.
2. State of the Art
In the fabrication of semiconductor packages, semiconductor dice (also known as xe2x80x9csemiconductor devicesxe2x80x9d or xe2x80x9csemiconductor chipsxe2x80x9d) are typically mounted and electrically connected to carrier substrates appropriate for the chip type and the subsequent use of the package. For example, chip-on-board (COB), board-on-chip (BOC), ball grid array (BGA), chip-scale, or leads-over-chip (LOC) mounting arrangements may be made on printed circuit board strips, tape frames and other carrier substrates known in the art. After die attach (the mounting of the semiconductor die to the carrier substrate), the hybrid combination of components is electrically connected, generally through wire bonding, conductive adhesives or solder reflow, then encapsulated for protection. The finished package is then made available for use in a wide variety of applications.
Semiconductor dice and carrier substrates are distinct components which are manufactured by separate processes. Individual integrated circuit dice are usually formed from a larger structure known as a semiconductor wafer, which is typically comprised primarily of silicon, although other materials such as gallium arsenide and indium phosphide are also sometimes used. Each semiconductor wafer has a plurality of integrated circuit semiconductor dice and/or circuitry, arranged in rows and columns with the periphery of each integrated circuit being substantially rectangular in shape, the integrated circuits of the semiconductor die being formed through a combination of deposition, etching, and photo-lithographic techniques. The inactive silicon backsides of the wafers are typically thinned (i.e., have their cross sections reduced) by a mechanical and/or chemical grinding process, and the wafers sawed or xe2x80x9cdicedxe2x80x9d into substantially rectangularly-shaped discrete integrated circuit semiconductor dice. The nature and complexity of the process for fabricating integrated circuits make the manufacturing cost of an individual semiconductor die relatively high.
With respect to the various carrier substrates for COB, BOC, BGA, LOC, chip-scale, and other types of packages, each of the carrier substrates is generally manufactured with several common features: an attachment site for at least one semiconductor die, a plurality of bond pads and conductive traces for interconnecting conductors on one or more semiconductor dice, a resist or insulating layer for electrically isolating the conductive traces and interconnections, tooling holes on the substrate edges for automated machine handling, and alignment marks for semiconductor die placement, wire bonding, and substrate orientation. The electronic properties and performance of the carrier substrate are determined by precise characteristics of the conductive layers and insulation layers which form it, including the composition, thickness, and surface quality of the various types of layers.
Currently, many carrier substrates (also referred to as xe2x80x9cmounting substratesxe2x80x9d) have multiple die-attach sites per carrier strip, which may further be formed in an array arrangement of several across. Such high-density arrays are suitable for increased throughput in automated processing, such as die-attach processing, as well as desirable for use in various electronics applications. For example, arrays of three rows of three semiconductor die sites across are commonly used on a single printed circuit board strip. An exemplary array for a BGA-type carrier substrate 1 is shown in drawing FIG. 1. Semiconductor die sites 10, for mounting and electrical attachment of a semiconductor die, are configured in an arrangement of three across the substrate strip. Pin one indicators 11 and fiducial marks 12, which provide orientation for vision systems associated with automated machine handling and semiconductor die placement apparatus (not shown), are formed as openings in a layer of solder resist 3 on carrier substrate 1. Semiconductor die sites 10 are shown with solder balls 16 of the BGA surrounding each semiconductor die receiving area 14 with solder balls 16 configured in a ball grid array arrangement 54. The solder balls 16 are typically placed on contact pads (not shown), which are further electrically interconnected to circuit traces (not shown) underlying a passivation layer of solder resist 3 on the surface of the carrier substrate 1. The circuit traces are, in turn, electrically connected to other contact pads within or immediately proximate semiconductor die sites 10.
After die attach, conductive wires extending from the active surface of the mounted semiconductor die are typically wire bonded onto the contact pads in the die site of the carrier substrate 1. The conductive traces, contact pads, and other contact pads are typically formed by laminating or depositing a metal material (e.g., copper) onto a base insulating substrate material. Subsequent photo-lithographic and etching techniques are then used to define the actual conductive patterns.
Referring again to drawing FIG. 1, carrier substrate 1 also includes a layer of solder resist 3. The layer of solder resist 3 is applied using photo-lithographic processes onto carrier substrate 1, and serves to mask or shield conductive members on the top and bottom carrier substrate surfaces during subsequent soldering and/or plating processes and/or various other processes. Various solder resist materials are well known and commercially available for such processes. With respect to the surface of carrier substrate 1, solder resist layer 3 masks all portions of the surface except the semiconductor die sites 10 and the contact pads for placement of solder balls 16. As previously described, pin one indicator 11 and fiducial marks 12 are typically formed as openings in solder resist layer 3 subsequent to the deposition of solder resist layer 3. Any conductive elements within semiconductor die site 10 thus remain exposed, as does at least a portion of the contact pads, after application of solder resist layer 3 to the top surface of the carrier substrate 1.
In the process of die attach, a die-attach apparatus typically uses a vision system to locate a fiducial mark, pin one indicator, and/or any other alignment feature on the lead frame or other mounting substrate. Using an X-Y table for proper alignment, the vision system checks the semiconductor die position on the die pickup tool and directs the apparatus to adjust the substrate and die pickup tool into the correct positions for precise semiconductor die placement. Typically, semiconductor dice are presented to a die-attach apparatus in sawed wafer form and are mounted on wafer tape for attachment on metal lead frames or any suitable substrate. For some die-attach apparatus, semiconductor dice may also be presented in gel or waffle pack form for attachment to the desired substrate. In the die-bonding process, semiconductor dice are selectively picked from those of wafers respectively probe-tested in their manufacturing factories using various testing equipment. To orient the semiconductor dice, the die bonder""s vision system identifies a feature on a die and directs the X-Y table to pick up and align the die in the X, Y, and theta directions. Meanwhile, a mounting substrate has been indexed to the die-attach site and properly oriented. At the die-attach site, a precise amount of adhesive, such as epoxy resin, is applied. The picked-up die is then bonded to the die-attach site of the mounting substrate via the adhesive.
Since semiconductor dice are high-grade products with highly integrated structures, the cost per semiconductor die may be high. Prior art die-attach processes, however, tend to focus on methods of dealing with defective semiconductor dice and not defective die sites on a mounting substrate. For this reason, it is desirable to classify, map and selectively reject defective die sites of substrates prior to the mounting of functional semiconductor dice thereat.
In each batch of manufactured semiconductor dice and substrate components, a small percentage of the substrate components will be defective. In an effort to minimize the costs and maximize the quality of assembled packages, steps are typically taken to ensure that only semiconductor dice and substrate components which are found to be functional are assembled with one another. Therefore, prior to the die attachment process, wafers, semiconductor dice and carrier substrates are typically tested for electrical defects, contamination, and other irregularities. Semiconductor dice and substrates that are found to be defective are typically marked in a manner so as to distinguish them from known good components.
There are numerous teachings relating to the marking and/or mapping of defects in semiconductor wafers and semiconductor dice. One method for marking used extensively in the semiconductor industry is to use colored ink dots to label semiconductor dice which have failed testing procedures. These ink dots can be read by a vision system for automated pick-and-place processing. For example, U.S. Pat. No. 5,654,204 to Anderson discloses a process in which a wafer is electronically mapped, individual semiconductor dice are tested, and a wafer map identifying the defective semiconductor dice is produced and provided to an automated inking apparatus.
In U.S. Pat. No. 5,256,5789 to Corley et al., a method for wafer map recording is disclosed wherein individual active dice are tested for functionality while in wafer form. The active dice are then categorized based on functional results, and the testing results are summarized on a wafer map. A binary code is then generated which contains the entire wafer map information. This information is recorded on the semiconductor wafer by laser scribing, and the results used for either manual or automated die selection.
In U.S. Pat. No. 6,021,380 to Fredriksen et al., a scanner is employed to produce a virtual image of the wafer, identifying all chips even when diced apart. A vision system uses the virtual wafer image to sort out defective chips, and gross defects identified by the vision system process are classified and marked in a computer-stored wafer map.
Various patents, such as U.S. Pat. No. 5,175,425 to Spratte et al., U.S. Pat. No. 4,585,931 to Duncan et al., and U.S. Pat. No. 4,510,673 to Shils et al., are directed to assorted other semiconductor marking techniques. The patents to Spratte et al. and Duncan et al. disclose processes for laser marking and identifying semiconductor wafers with a machine readable bar code, while the patent to Shils et al. discloses a method of laser marking the backside of individual dice with a unique identifying code.
The prior art of identifying and marking defective carrier substrates is less expansive than the art dealing with defective semiconductor wafers or dice. When irregularities are found on individual die sites of a carrier substrate strip, the entire strip is ordinarily not rendered unusable unless a substantial number of the die sites are found to be defective. For some strips, defective sites constituting 10% or greater of the total of die sites will justify discarding the entire strip. In other strip arrays, higher numbers of defective die sites are tolerated. When a defective die site is identified on a substrate, typically by automated testing apparatus or a vision system, conventional practice is for an operator to manually xe2x80x9cx-outxe2x80x9d or xe2x80x9cink-outxe2x80x9d a feature of the defective die site, rendering the feature xe2x80x9cunreadablexe2x80x9d by the vision recognition system of an automatic die-bonding apparatus. A relatively simple system of vision recognition is a black and white digital recognition system (DRS), which can recognize inked-out features and streets between die-attach sites. In more sophisticated operations, a pattern recognition system (PRS) is used as a vision system to identify defects and to recognize inked-out features. The PRS can also be used to align a bond pad with a die.
The xe2x80x9cinking outxe2x80x9d is usually accomplished by marking over an exposed feature in the solder resist which is a component of the defective die site, completing the mark with an ink pen, for example. As used herein, the term xe2x80x9cexposed featurexe2x80x9d denotes an opening in the solder resist which typically exposes a visibly discernable Au/Ni/Cu surface. Features which are commonly xe2x80x9cinked outxe2x80x9d include pin one indicators, bond pads, and/or fiduciary marks. Illustrated in drawing FIG. 2 is a BGA substrate strip of drawing FIG. 1 with multiple die sites 10, wherein a substrate area around die site 10a is shown containing a conventional inked-out feature consisting of an inked-out pin one indicator 11a. 
When an array with one or more xe2x80x9cinked-outxe2x80x9d die sites is placed in an automated die-attach apparatus, data from the digital or pattern recognition system and/or testing systems is fed into a processor, the processor interpreting the data to instruct the die-attach apparatus to skip over the defective die sites.
There are, however, potential problems associated with identifying defective die sites by manually inking-out one or more features. First, the small size of the die sites and the features thereon make it difficult for an operator to perform the xe2x80x9cink-outxe2x80x9d step on a defective site without marking through features of other xe2x80x9cgoodxe2x80x9d die sites nearby. Secondly, the ink from a mark may bleed, smear, or spray in some cases, thereby causing contamination of adjacent die sites. Additionally, the manual marking of defective sites is a relatively slow process. By automating the marking process, throughput could be increased substantially, and the potential for substrate contamination and operator error substantially reduced.
It is also the case, however, that automated processes for the marking of defective substrates have been known in the art. U.S. Pat. No. 4,437,229 to Bitler et al. discloses a method of marking defective electronic articles in an array arrangement. The method entails forming film circuit articles in the array with added test pads and resistive elements, and electrically altering a resistive element to a relatively high resistive value when a defective circuit is found. The article substrate (an array of film circuits) is subsequently fed into a holding apparatus which measures the resistive value of the resistive element, thereby labeling the substrate as acceptable or defective. The holder then transfers this data to a microprocessor within a die-bonding apparatus. The die bonder then directs chips to be bonded only to those array circuits which have been labeled as functional by virtue of their low resistive values.
U.S. Pat. No. 4,787,143 to Yagi et al. discloses a method for applying a code mark to a substrate to which electronic parts are to be mounted. The code mark, which may be a bar code, is formed on the substrate prior to the mounting of a semiconductor die. Once the semiconductor die is mounted on the substrate, a mounting failure detection mechanism on a die mounting apparatus serves to automatically detect an incorrect or defective mounting of the die. The mounting failure detection system is further configured with a code reader for reading the code mark of each substrate and a control box for generating mounting failure data. Yagi et al. teaches that when a mounting failure has been detected, a mounting failure data edit controller collates mounting failure data supplied from the control box with the code signals from the code reader, then uses the data to classify and automatically separate defective substrates from good ones.
U.S. Pat. No. 5,197,650 to Monzen et al. teaches placing an identifier, preferably a bar code, on a lead frame prior to the mounting of semiconductor dice. Semiconductor dice are first tested, then mounted to the lead frame. As the dice are mounted, an information processing unit adds information about the lead frame to the semiconductor die test results. The accumulated data is then forwarded to the next phase of the packaging process, which may be wire bonding, for example. The wire bonding apparatus receives the combined data and uses it accordingly to perform wire bonding operations. Monzen et al., however, does not teach that the bar code contains information about defective semiconductor die sites. Instead, Monzen et al. teaches that all the dice, even the defective ones, are mounted to the lead frame, and that the identifying information on the bar-coded lead frame is combined with the semiconductor die test results to be employed at later stages after semiconductor die bonding.
As can be seen from the foregoing, the method of manually inking-out a defective semiconductor die site is troublesome and inefficient. Furthermore, the prior art automated processes dealing with defective carrier substrates either allow the attachment of the semiconductor die to a defective site, thus sacrificing a good semiconductor die, or, in the case of U.S. Pat. No. 4,437,229 to Bitler et al., require the additional steps of adding a test pad and a resistive element to the circuits on the substrate. Accordingly, what is needed in the art is a method of marking a defective semiconductor die site which is automated, accurate, low cost, relatively simple, and has high throughput. In addition to the foregoing characteristics, a marking method is needed which can be read by die-bonding apparatus to ensure that only functional semiconductor die sites are provided with semiconductor dice.
The present invention comprises methods and apparatus relating to the marking and identification of defective semiconductor die sites on a mounting substrate prior to die attach. In this regard, a mounting substrate is provided and inspected and tested for visual and electrical defects. The inspection and testing data are then compiled and correlated with individual semiconductor die sites. Information relating to the functionality and/or various defects of one or more semiconductor die sites is then encoded in the form of a designator. The information encoded on the designator may then be read or scanned by, for example, computer-driven video equipment, and then processed for use in a die-attach process to place semiconductor dice only on known good die (KGD) sites, as indicated by the inspection and testing data.
Preferably, the designator of the present invention is located externally from each die site area of a mounting substrate. In one embodiment, the designator is located on an unused peripheral surface portion of a mounting substrate. The designator preferably comprises information encoded in the form of a bar code, or series of identifying marks. The designator also preferably comprises a strip of magnetic tape with information programmed thereon. In a further embodiment, the compiled inspection and test information can be correlated with individual semiconductor die sites and a particular substrate configuration to create a computerized map of a mounting substrate. Data relating to defective semiconductor die sites on the substrate can thus be stored in computer memory and transferred electronically to a die-bonding station in furtherance of a die-attach process.
In addition to information concerning the functionality of semiconductor die sites on a substrate, the information encoded on the designator may include manufacturing information, such as the various process specifications used in forming the mounting substrate. The encoded information may also include testing specifications and parameters, as well as identifying information, such as lot number, and time, date and place of manufacture, etc. When scanned or read by a computer, this information can be used, for example, in fault verification and fault isolation analysis.
The present invention takes up no real estate on a semiconductor die site, and thus is particularly advantageous when used in combination with substrate arrays for producing chip scale, or near chip scale, packages. The invention also requires no openings in the solder resist of an individual semiconductor device package, thus allowing for a more planar solder resist surface for clamping to reduce resin bleed during a mold encapsulation process. The present invention further avoids the problems inherent in xe2x80x9cinking-outxe2x80x9d the very small unique features on semiconductor die sites, including problems associated with operator error and ink contamination due to ink bleeding, smearing, or spraying. Finally, the present invention provides for a completely automated process of identifying and recording multiple defective semiconductor die sites on a substrate, thus allowing throughput to be increased substantially.
Other features and advantages of the present invention will become apparent to those of skill in the art through a consideration of the ensuing description, the accompanying drawings, and the appended claims.